1. Field of the Invention
This invention relates generally to phase-locked loop circuits and, more particularly, is directed to a phase-locked loop circuit for use with a demodulating circuit of an AM stereophonic receiver.
2. Description of the Prior Art
Systems for transmitting and receiving AM stereo signals are known in the art. In such systems, a phase-locked loop (PLL) circuit is provided in the stereo demodulating circuit of the AM stereophonic receiver to produce a pure carrier or non-modulation component of the received input signal by attenuating a side band component of the input signal. Accordingly, the response frequency of the PLL circuit is generally set in a lower frequency range of the modulation frequency of the signal, for example, in the range of 20-50 Hz. Accordingly, because of this so-called capture range of the PLL circuit, or when the frequency of the received input signal is changed from the condition where the PLL circuit is not locked, the variable range of the oscillating frequency produced by a voltage-controlled oscillator(VCO) in the PLL circuit which can be locked to such input signal becomes extremely narrow. As a result, manual tuning for the AM stereophonic signal becomes quite difficult and the locked state of the circuit may become lost by changes in temperature, vibration and the like.
Accordingly, it has been proposed to provide a lock detecting circuit which produces a lock detected output signal when the PLL circuit is in its locked state. This lock detected output signal is used to switch the PLL circuit such that the latter has a large capture range of, for example, 5-10 KHz when the locked condition of the PLL circuit is lost and has a narrow capture range within a predetermined frequency band, as aforementioned, when the locked condition of the PLL circuit is operative. In particular, the lock detected output signal is supplied through a switch and a low-pass filter to the VCO to vary the oscillating frequency generated thereby. The switch is changed over to different resistances in accordance with the switching state to control the VCO during the locked and unlocked (released) states. The ratio of the resistances associated with the different contacts of the switch is approximately 500:1, which varies the response frequency of the PLL circuit from the range of 20 Hz-10 KHz to the range of 20-50 Hz. Accordingly, it should be appreciated that the loop gain of the PLL circuit must be changed over a wide range which requires strict adherence to the resistance values of the switch and control of any leakage resistance at the switch. In addition, if the switch has a serial offset, the locked state of the PLL circuit may sometimes be released during the switching operation if the switch timing is unsatisfactory. For this reason, it is extremely difficult to construct an analog switch as a bipolar linear IC (integrated circuit). Accordingly, to avoid this problem, MOSFETs and the like must be provided at the output of the integrated circuit, making manufacture of the PLL circuit expensive.